Conventionally, a CPU integrated circuit which is a CPU has access to two forms of memory: a first memory (“data cache”) within the CPU, and an external memory stored on one or more memory chips. The processor of the CPU is able to access the data cache more quickly than the external memory, but the capacity of the data cache is smaller than that of the external memory, and for many calculations the CPU requires the full capacity of the external memory. For this reason, the data cache is arranged to store a duplicate of the data in the external memory. The processor can then access the data cache when it requires the duplicated data, and the external memory when it requires data which is not duplicated in the internal memory.
The configuration is illustrated in FIG. 1 which shows that when the processor 1 of the CPU 3 needs to access data with a given address it does so via a cache controller 5 which determines whether the data with that address is stored in the data cache 7. If so, the data is read from there. If not, the data is read from external memory 9 (which may take the form of one or more memory chips) using a system bus 11. Once the CPU 3 reads data from the external memory 9, the data will be mirrored in the data cache 7, and the next read access from the same location in the external memory 9 will be skipped and instead the data will be taken from the data cache 7. When the processor writes data into the data cache 7 it is not normally copied into the external memory 9 at once, but instead written into the external memory 9 when the corresponding data in the data cache 7 is going to be replaced. Note that the system of FIG. 1 normally includes an address decoder (not shown) which is involved in passing the signals between the CPU 3 and the external memory 9. This address decoder (not shown) is employed because the external memory 9 may be partitioned, and the address decoder defines a mapping between the address in the CPU memory space and an address in the external memory 9. For example, when the CPU 3 issues a write instruction the decoder converts the output address of the CPU 3 in the memory space of the CPU into the address of the corresponding location in the partitioned external memory 9.
The memory address map of the system of FIG. 1 in the memory space of the CPU is illustrated in FIG. 2. All of this memory corresponds to addresses in the external memory 9 (under the mapping defined by the decoder). The address space includes a “memory” section 4 which the processor 1 employs as the read/write memory for performing its operations (varying portions of this memory space are mirrored in the data cache 7), and a “reserved” section 6 which is an area of memory which is not in fact required for performing calculations.